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Stack Module Features
* * * *
64-Mbit Flash + 16-Mbit PSRAM Power Supply of 2.7V to 3.1V Data I/O x16 66-ball CBGA Package: 8 x 11x 1.0 mm
64-Mbit Flash Features
* 64-megabit (4M x 16) Flash Memory * 2.7V - 3.1V Read/Write * High Performance * * *
- Asynchronous Access Time - 70, 85 ns Sector Erase Architecture - Eight 4K Word Sectors with Individual Write Lockout - 32K Word Main Sectors with Individual Write Lockout Typical Sector Erase Time: 32K Word Sectors - 500 ms; 4K Word Sectors - 100 ms 64M, Four Plane Organization, Permitting Concurrent Read in Any of Three Planes not Being Programmed/Erased - Memory Plane A: 16M of Memory Including Eight 4K Word Sectors - Memory Plane B: 16M of Memory Consisting of 32K Word Sectors - Memory Plane C: 16M of Memory Consisting of 32K Word Sectors - Memory Plane D: 16M of Memory Consisting of 32K Word Sectors Suspend/Resume Feature for Erase and Program - Supports Reading and Programming Data from Any Sector by Suspending Erase of a Different Sector - Supports Reading Any Word by Suspending Programming of Any Other Word Low-power Operation - 30 mA Active - 35 A Standby 1.8V I/O Option Reduces Overall System Power Data Polling and Toggle Bit for End of Program Detection VPP Pin for Write Protection and Accelerated Program/Erase Operations RESET Input for Device Initialization Top or Bottom Boot Block Configuration Available 128-bit Protection Register Common Flash Interface (CFI)
64-Mbit Flash, 16-Mbit PSRAM (x16 I/O) AT52BC6402A AT52BC6402AT Preliminary
*
* * * * * * * *
16-Mbit PSRAM Features
* 16-Mbit (1M x 16) * 2.7V to 3.1V VCC Operation * 70 ns Access Time
Stack Module Description
The AT52BC6402A(T) consists of a 64-Mbit Flash stacked with a 16-Mbit PSRAM in a single CBGA package.
Stack Module Memory Contents
Device AT52BC6402A(T) Memory Combination 64M Flash + 16M PSRAM Flash/PSRAM Read Access Asynchronous, Page Mode
Rev. 3441B-STKD-11/04
1
66C4 - CBGA
Top View
A
1
2
3
4
5
6
7
8
9
10
11
12
NC
NC
A20 A16
A11 A8
A15 A10 A21
A14 A9
A13
A12
GND
NC I/O7 I/O5
NC
NC
B
I/O15 PSWE I/O14 I/O13 I/O12 A19 PSOE A7 A4 A6 A0 I/O11 I/O9 A3 CE1 I/O6 I/O4
C
WE
D
PSGND RESET PSCS PSVCC VCC I/O10 I/O8 A2 GND I/O2 I/O0 A1 OE I/O3 I/O1 PSCE1 NC NC NC
E
WP VPP UB A17 A5
F
LB
G
A18
H
NC NC NC
Pin Configurations
Pin Name A0 - A21 I/O0 - I/O15 CE1 PSCE1 PSCS OE/PSOE WE/PSWE LB UB RESET WP VPP VCC/PSVCC NC GND/PSGND Function Address Data Inputs/Outputs Flash Chip Enable PSRAM Chip Enable PSRAM Chip Select (Deep Power-down Control - Mode Pin) Flash Output Enable/PSRAM Output Enable Flash Write Enable/PSRAM Write Enable Lower Byte Control (PSRAM) Upper Byte Control (PSRAM) Flash Reset Flash Write Protect Flash Write Protection and Power Supply for Accelerated Program/Erase Operation Flash Power Supply/PSRAM Power Supply No Connect Device Ground/PSRAM Ground
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64-Mbit Flash Description
The 64-Mbit Flash memory is divided into multiple sectors and planes for erase operations. The devices can be read or reprogrammed off a single 2.7V power supply, making them ideally suited for in-system programming. The 64-Mbit device is divided into four memory planes. A read operation can occur in any of the three planes which is not being programmed or erased. This concurrent operation allows improved system performance by not requiring the system to wait for a program or erase operation to complete before a read is performed. To further increase the flexibility of the device, it contains an Erase Suspend and Program Suspend feature. This feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors. There is no reason to suspend the erase or program operation if the data to be read is in another memory plane. The end of program or erase is detected by Data Polling or toggle bit. The VPP pin provides data protection and faster programming and erase times. When the VPP input is below 0.8V, the program and erase functions are inhibited. When VPP is at 1.65V or above, normal program and erase operations can be performed. With VPP at 12.0V, the program and erase operations are accelerated. With VPP at 12V, a six-byte command (Enter Single Pulse Program Mode) to remove the requirement of entering the three-byte program sequence is offered to further improve programming time. After entering the six-byte code, only single pulses on the write control lines are required for writing into the device. This mode (Single Pulse Word Program) is exited by powering down the device, by taking the RESET pin to GND or by a high-to-low transition on the VPP input. Erase, Erase Suspend/Resume, Program Suspend/Resume and Read Reset commands will not work while in this mode; if entered they will result in data being programmed into the device. It is not recommended that the six-byte code reside in the software of the final product but only exist in external programming code.
Device Operation
COMMAND SEQUENCES: The device powers on in the read mode. Command sequences are used to place the device in other operating modes such as program and erase. After the completion of a program or an erase cycle, the device enters the read mode. The command sequences are written by applying a low pulse on the WE input with CE low and OE high or by applying a low-going pulse on the CE input with WE low and OE high. The address is latched on the falling edge of the WE or CE pulse whichever occurs first. Valid data is latched on the rising edge of the WE or the CE pulse, whichever occurs first. The addresses used in the command sequences are not affected by entering the command sequences. ASYNCHRONOUS READ: The 64-Mbit Flash is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET pin halts the present device operation and puts the outputs of the device in a high-impedance state. When a high level is reasserted on the RESET pin, the device returns to read or standby mode, depending upon the state of the control pins.
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ERASE: Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a logical "1". The entire memory can be erased by using the Chip Erase command or individual planes or sectors can be erased by using the Plane Erase or Sector Erase commands. CHIP ERASE: Chip Erase is a six-bus cycle operation. The automatic erase begins on the rising edge of the last WE pulse. Chip Erase does not alter the data of the protected sectors. After the full chip erase the device will return back to the read mode. The hardware reset during Chip Erase will stop the erase but the data will be of unknown state. Any command during Chip Erase except Erase Suspend will be ignored. PLANE ERASE: As a alternative to a full chip erase, the device is organized into four planes that can be individually erased. The plane erase command is a six-bus cycle operation. The plane whose address is valid at the sixth falling edge of WE will be erased provided none of the sectors within the plane are protected. SECTOR ERASE: As an alternative to a full chip erase or a plane erase, the device is organized into multiple sectors that can be individually erased. The Sector Erase command is a six-bus cycle operation. The sector whose address is valid at the sixth falling edge of WE will be erased provided the given sector has not been protected. WORD PROGRAMMING: The device is programmed on a word-by-word basis. Programming is accomplished via the internal device command register and is a four-bus cycle operation. The programming address and data are latched in the fourth cycle. The device will automatically generate the required internal programming pulses. Please note that a "0" cannot be programmed back to a "1"; only erase operations can convert "0"s to "1"s. FLEXIBLE SECTOR PROTECTION: The 64-Mbit device offers two sector protection modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector protection for sectors whose content changes frequently. The Hardlock protection mode is recommended for sectors whose content changes infrequently. Once either of these two modes is enabled, the contents of the selected sector is read-only and cannot be erased or programmed. Each sector can be independently programmed for either the Softlock or Hardlock sector protection mode. At power-up and reset, all sectors have their Softlock protection mode enabled. SOFTLOCK AND UNLOCK: The Softlock protection mode can be disabled by issuing a two-bus cycle Unlock command to the selected sector. Once a sector is unlocked, its contents can be erased or programmed. To enable the Softlock protection mode, a sixbus cycle Softlock command must be issued to the selected sector. HARDLOCK AND WRITE PROTECT (WP): The Hardlock sector protection mode operates in conjunction with the Write Protection (WP) pin. The Hardlock sector protection mode can be enabled by issuing a six-bus cycle Hardlock software command to the selected sector. The state of the Write Protect pin affects whether the Hardlock protection mode can be overridden. * When the WP pin is low and the Hardlock protection mode is enabled, the sector cannot be unlocked and the contents of the sector is read-only. * When the WP pin is high, the Hardlock protection mode is overridden and the sector can be unlocked via the Unlock command. To disable the Hardlock sector protection mode, the chip must be either reset or power cycled.
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Table 1. Hardlock and Softlock Protection Configurations in Conjunction with WP
Hardlock 0 0 1 Softlock 0 1 1 Erase/ Prog Allowed? Yes No No
VPP VCC/5V VCC/5V VCC/5V
WP 0 0 0
Comments No sector is locked Sector is Softlocked. The Unlock command can unlock the sector. Hardlock protection mode is enabled. The sector cannot be unlocked. No sector is locked. Sector is Softlocked. The Unlock command can unlock the sector. Hardlock protection mode is overridden and the sector is not locked. Hardlock protection mode is overridden and the sector can be unlocked via the Unlock command. Erase and Program Operations cannot be performed.
VCC/5V VCC/5V VCC/5V
1 1 1
0 0 1
0 1 0
Yes No Yes
VCC/5V
1
1
1
No
VIL
x
x
x
No
Figure 1. Sector Locking State Diagram
UNLOCKED LOCKED
[000]
A
B
[001]
C
WP = VIL = 0
C
[011]
Power-Up/Reset Default
Hardlocked
[110]
A C A B
B
[111]
Hardlocked is disabled by WP = VIH
WP = VIH = 1
C
Power-Up/Reset Default
[100]
[101]
A = Unlock Command B = Softlock Command C = Hardlock Command
Note:
1. The notation [X, Y, Z] denotes the locking state of a sector. The current locking state of a sector is defined by the state of WP and the two bits of the sector-lock status D[1:0].
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SECTOR PROTECTION DETECTION: A software method is available to determine if the sector protection Softlock or Hardlock features are enabled. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from the I/O0 and I/O1 at address location 00002H within a sector will show if the sector is unlocked, softlocked, or hardlocked. Table 2. Sector Protection Status
I/O1 0 0 1 1 I/O0 0 1 0 1 Sector Protection Status Sector Not Locked Softlock Enabled Hardlock Enabled Both Hardlock and Softlock Enabled
PROGRAM/ERASE STATUS: The device provides several bits to determine the status of a program or erase operation: I/O2, I/O3, I/O5, I/O6, and I/O7. All other status bits are don't care. Table 3 on page 11 and the following four sections describe the function of these bits. To provide greater flexibility for system designers, the 64-Mbit device contains a programmable configuration register. The configuration register allows the user to specify the status bit operation. The configuration register can be set to one of two different values, "00" or "01". If the configuration register is set to "00", the part will automatically return to the read mode after a successful program or erase operation. If the configuration register is set to a "01", a Product ID Exit command must be given after a successful program or erase operation before the part will return to the read mode. It is important to note that whether the configuration register is set to a "00" or to a "01", any unsuccessful program or erase operation requires using the Product ID Exit command to return the device to read mode. The default value (after power-up) for the configuration register is "00". Using the four-bus cycle set configuration register command as shown in the Command Definition table on page 12, the value of the configuration register can be changed. Voltages applied to the reset pin will not alter the value of the configuration register. The value of the configuration register will affect the operation of the I/O7 status bit as described below. DATA POLLING: The 64-Mbit device features Data Polling to indicate the end of a program cycle. If the status configuration register is set to a "00", during a program cycle an attempted read of the last word loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to read the device will give a "0" on I/O7. Once the program or erase cycle has completed, true data will be read from the device. Data Polling may begin at any time during the program cycle. Please see Table 3 on page 11 for more details. If the status bit configuration register is set to a "01", the I/O7 status bit will be low while the device is actively programming or erasing data. I/O7 will go high when the device has completed a program or erase operation. Once I/O7 has gone high, status information on the other pins can be checked. The Data Polling status bit must be used in conjunction with the erase/program and VPP status bit as shown in the algorithm in Figures 2 and 3. TOGGLE BIT: In addition to Data Polling, the 64-Mbit device provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the memory will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling
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and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. Please see Table 3 on page 11 for more details. The toggle bit status bit should be used in conjunction with the erase/program and VPP status bit as shown in the algorithm in Figures 4 and 5 on page 10. ERASE/PROGRAM STATUS BIT: The device offers a status bit on I/O5 that indicates whether the program or erase operation has exceeded a specified internal pulse count limit. If the status bit is a "1", the device is unable to verify that an erase or a word program operation has been successfully performed. The device may also output a "1" on I/O5 if the system tries to program a "1" to a location that was previously programmed to a "0". Only an erase operation can change a "0" back to a "1". If a program (Sector Erase) command is issued to a protected sector, the protected sector will not be programmed (erased). The device will go to a status read mode and the I/O5 status bit will be set high, indicating the program (erase) operation did not complete as requested. Once the erase/program status bit has been set to a "1", the system must write the Product ID Exit command to return to the read mode. The erase/program status bit is a "0" while the erase or program operation is still in progress. Please see Table 3 on page 11 for more details. VPP STATUS BIT: The 64-Mbit device provides a status bit on I/O3 that provides information regarding the voltage level of the VPP pin. During a program or erase operation, if the voltage on the VPP pin is not high enough to perform the desired operation successfully, the I/O3 status bit will be a "1". Once the VPP status bit has been set to a "1", the system must write the Product ID Exit command to return to the read mode. On the other hand, if the voltage level is high enough to perform a program or erase operation successfully, the VPP status bit will output a "0". Please see Table 3 on page 11 for more details. ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to interrupt a sector erase operation and then program or read data from a different sector within the same plane. Since this device has a multiple plane architecture, there is no need to use the erase suspend feature while erasing a sector when you want to read data from a sector in another plane. After the Erase Suspend command is given, the device requires a maximum time of 15 s to suspend the erase operation. After the erase operation has been suspended, the plane that contains the suspended sector enters the erase-suspend-read mode. The system can then read data or program data to any other sector within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the system must write the Erase Resume command. The Erase Resume command is a one-bus cycle command, which does require the plane address. The device also supports an erase suspend during a complete chip erase. While the chip erase is suspended, the user can read from any sector within the memory that is protected. The command sequence for a chip erase suspend and a sector erase suspend are the same. PROGRAM SUSPEND/PROGRAM RESUME: The Program Suspend command allows the system to interrupt a programming operation and then read data from a different word within the memory. After the Program Suspend command is given, the device requires a maximum of 10 s to suspend the programming operation. After the programming operation has been suspended, the system can then read from any other word within the device. An address is not required during the program suspend operation. To resume the programming operation, the system must write the Program Resume command. The program suspend and resume are one-bus cycle commands. The command sequence for the erase suspend and program suspend are the same, and the command sequence for the erase resume and program resume are the same.
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128-BIT PROTECTION REGISTER: The 64-Mbit device contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number. The data in block B is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the four-bus cycle Program Protection Register command must be used as shown in the Command Definition table on page 12. To lock out block B, the four-bus cycle lock protection register command must be used as shown in the Command Definition table. Data bit D1 must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are don't cares. To determine whether block B is locked out, the status of Block B Protection command is given. If data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be reprogrammed. Please see the Protection Register Addressing Table on page 13 for the address locations in the protection register. To read the protection register, the Product ID Entry command is given followed by a normal read operation from an address within the protection register. After determining whether block B is protected or not or reading the protection register, the Product ID Exit command must be given prior to performing any other operation. CFI: Common Flash Interface (CFI) is a published, standardized data structure that may be read from a Flash device. CFI allows system software to query the installed device to determine the configurations, various electrical and timing parameters, and functions supported by the device. CFI is used to allow the system to learn how to interface to the Flash device most optimally. The two primary benefits of using CFI are ease of upgrading and second source availability. The command to enter the CFI Query mode is a one-bus cycle command which requires writing data 98h to address 55h. The CFI Query command can be written when the device is ready to read data or can also be written when the part is in the product ID mode. Once in the CFI Query mode, the system can read CFI data at the addresses given in Table 4 on page 24. To exit the CFI Query mode, the product ID exit command must be given. If the CFI Query command is given while the part is in the product ID mode, then the product ID exit command must first be given to return the part to the product ID mode. Once in the product ID mode, it will be necessary to give another product ID exit command to return the part to the read mode. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the 64-Mbit device in the following ways: (a) VCC sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) V CC power-on delay: once VCC has reached the V CC sense level, the device will automatically time-out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. (e) VPP is less than VILPP. INPUT LEVELS: While operating with a 2.7V to 3.1V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can be driven from 0 to VCCQ + 0.6V.
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Figure 2. Data Polling Algorithm (Configuration Register = 00) Figure 3. Data Polling Algorithm (Configuration Register = 01)
START
START
Read I/O7 - I/O0 Addr = VA
Read I/O7 - I/O0 Addr = VA
YES I/O7 = Data? NO NO
NO I/O7 = 1?
YES NO
I/O3, I/O5 = 1?
I/O3, I/O5 = 1?
YES Read I/O7 - I/O0 Addr = VA
YES Program/Erase Operation Not Successful, Write Product ID Exit Command Program/Erase Operation Successful, Write Product ID Exit Command
I/O7 = Data?
YES
NO Program/Erase Operation Not Successful, Write Product ID Exit Command Program/Erase Operation Successful, Device in Read Mode
Note:
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address.
Notes:
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. I/O7 should be rechecked even if I/O5 = "1" because I/O7 may change simultaneously with I/O5.
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Figure 4. Toggle Bit Algorithm (Configuration Register = 00)
Figure 5. Toggle Bit Algorithm (Configuration Register = 01)
START
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Toggle Bit = Toggle? YES NO I/O3, I/O5 = 1?
NO
Toggle Bit = Toggle? YES NO I/O3, I/O5 = 1?
NO
YES Read I/O7 - I/O0 Twice
YES Read I/O7 - I/O0 Twice
Toggle Bit = Toggle? YES Program/Erase Operation Not Successful, Write Product ID Exit Command
NO
Toggle Bit = Toggle? YES
NO
Program/Erase Operation Successful, Device in Read Mode
Program/Erase Operation Not Successful, Write Product ID Exit Command
Program/Erase Operation Successful, Write Product ID Exit Command
Note:
1. The system should recheck the toggle bit even if I/O5 = "1" because the toggle bit may stop toggling as I/O5 changes to "1".
Note:
1. The system should recheck the toggle bit even if I/O5 = "1" because the toggle bit may stop toggling as I/O5 changes to "1".
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Table 3. Status Bit Table
I/O7 Configuration Register: Read Address In While 00/01 Plane A 00/01 Plane B 00/01 Plane C 00/01 Plane D 00/01 Plane A 00/01 Plane B I/O6 00/01 Plane C 00/01 Plane D 00/01 Plane A 00/01 Plane B I/O2 00/01 Plane C 00/01 Plane D
Programming in Plane A Programming in Plane B Programming in Plane C Programming in Plane D Erasing in Plane A Erasing in Plane B Erasing in Plane C Erasing in Plane D Erase Suspended & Read Erasing Sector Erase Suspended & Read Nonerasing Sector Erase Suspended & Program Nonerasing Sector in Plane A Erase Suspended & Program Nonerasing Sector in Plane B Erase Suspended & Program Nonerasing Sector in Plane C Erase Suspended & Program Nonerasing Sector in Plane D
I/O7/0 DATA DATA DATA 0/0 DATA DATA DATA
DATA I/O7/0 DATA DATA DATA 0/0 DATA DATA
DATA DATA I/O7/0 DATA DATA DATA 0/0 DATA
DATA DATA DATA I/O7/0 DATA DATA DATA 0/0
TOGGLE DATA DATA DATA TOGGLE DATA DATA DATA
DATA TOGGLE DATA DATA DATA TOGGLE DATA DATA
DATA DATA TOGGLE DATA DATA DATA TOGGLE DATA
DATA DATA DATA TOGGLE DATA DATA DATA TOGGLE
1 DATA DATA DATA TOGGLE DATA DATA DATA
DATA 1 DATA DATA DATA TOGGLE DATA DATA
DATA DATA 1 DATA DATA DATA TOGGLE DATA
DATA DATA DATA 1 DATA DATA DATA TOGGLE
1
1
1
1
1
1
1
1
TOGGLE
TOGGLE
TOGGLE
TOGGLE
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
I/O7/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
DATA
I/O7/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
DATA
I/O7/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
DATA
I/O7/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
TOGGLE
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Command Definition (Hex)(1)
Command Sequence Read Chip Erase Plane Erase Sector Erase Word Program Dual-Word Program(8) Enter Single-pulse Program Mode Single-pulse Word Program Mode Sector Softlock Sector Unlock Sector Hardlock Erase/Program Suspend Erase/Program Resume Product ID Entry(7) Product ID Exit
(3)
Bus Cycles 1 6 6 6 4 5 6 1 6 2 6 1 1 3 3 1 4 4 4 4 1
1st Bus Cycle Addr Addr 555 555 555 555 555 555 Addr 555 555 555 xxx PA(6) 555 555 xxx 555 555 555 555 X55 Data DOUT AA AA AA AA AA AA DIN AA AA AA B0 30 AA AA FX AA AA AA AA 98
2nd Bus Cycle Addr Data
3rd Bus Cycle Addr Data
4th Bus Cycle Addr Data
5th Bus Cycle Addr Data
6th Bus Cycle Addr Data
AAA(2) AAA AAA AAA AAA AAA
55 55 55 55 55 55
555 555 555 555 555 555
80 80 80 A0 A1 80
555 555 555 Addr Addr0 555
AA AA AA DIN DIN0 AA
AAA AAA AAA
55 55 55
555 PA
(6)
10 20 30
SA(4)
Addr1 AAA
DIN1 55 555 A0
AAA SA(4) AAA
55 70 55
555
80
555
AA
AAA
55
SA(4)
40
555
80
555
AA
AAA
55
SA(4)(5)
60
AAA AAA
55 55
PA+00555 555
90 F0
Product ID Exit(3) Program Protection Register - Block B Lock Protection Register - Block B Status of Block B Protection Set Configuration Register CFI Query
AAA AAA AAA AAA
55 55 55 55
555 555 555 555
C0 C0 90 E0
xxxx(12)8x(11) xxxx80(12) xxxx80(13) xxx
DIN X0 DOUT(9) 00/01(10)
Notes:
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex). The ADDRESS FORMAT in each bus cycle is as follows: A11 - A0 (Hex), A11 - A21 (Don't Care). 2. Since A11 is a Don't Care, AAA can be replaced with 2AA. 3. Either one of the Product ID Exit commands can be used. 4. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 14 - 17 for details). 5. Once a sector is in the Hardlock protection mode, it cannot be disabled unless the chip is reset or power cycled. 6. PA is the plane address (A21 - A20). 7. During the fourth bus cycle, the manufacturer code is read from address PA+00000H, the device code is read from address PA+00001H, and the data in the protection register is read from addresses 000081H - 000088H. PA (A21 - A20) must specify the same plane address as specified in the third bus cycle. 8. The fast programming option enables the user to program two words in parallel only when VPP = 12V. The addresses, Addr0 and Addr1, of the two words, DIN0 and DIN1, must only differ in address A0. This command should be used for manufacturing purpose only. 9. If data bit D1 is "0", block B is locked. If data bit D1 is "1", block B can be reprogrammed. 10. The default state (after power-up) of the configuration register is "00". 11. Any address within the user programmable register region. Please see "Protection Register Addressing Table" on page 13. 12. For the AT49BV6416, xxxx = 0000H. For the AT49BV6416T, xxxx = 3F80H. 13. For the AT49BV6416, xxxx = 0000H. For the AT49BV6416T, xxxx = 0F80H.
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AT52BC6402A(T)
Absolute Maximum Ratings*
Temperature under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages Except VPP (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V VPP Input Voltage with Respect to Ground ......................................... 0V to 13.0V All Output Voltages with Respect to Ground ...........................-0.6V to VCCQ + 0.6V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Protection Register Addressing Table
Word 0 1 2 3 4 5 6 7 Use Factory Factory Factory Factory User User User User Block A A A A B B B B A7 1 1 1 1 1 1 1 1 A6 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 1 A2 0 0 0 1 1 1 1 0 A1 0 1 1 0 0 1 1 0 A0 1 0 1 0 1 0 1 0
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Memory Organization - 64-Mbit Bottom Boot
x16 Plane A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A B B B B B B Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 Size (Words) 4K 4K 4K 4K 4K 4K 4K 4K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 00000 - 00FFF 01000 - 01FFF 02000 - 02FFF 03000 - 03FFF 04000 - 04FFF 05000 - 05FFF 06000 - 06FFF 07000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF 58000 - 5FFFF 60000 - 67FFF 68000 - 6FFFF 70000 - 77FFF 78000 - 7FFFF 80000 - 87FFF 88000 - 8FFFF 90000 - 97FFF 98000 - 9FFFF A0000 - A7FFF A8000 - AFFFF B0000 - B7FFF B8000 - BFFFF C0000 - C7FFF C8000 - CFFFF D0000 - D7FFF D8000 - DFFFF E0000 - E7FFF E8000 - EFFFF F0000 - F7FFF F8000 - FFFFF 100000 - 107FFF 108000 - 10FFFF 110000 - 117FFF 118000 - 11FFFF 120000 - 127FFF 128000 - 12FFFF
Memory Organization - 64-Mbit Bottom Boot (Continued)
x16 Plane B B B B B B B B B B B B B B B B B B B B B B B B B B C C C C C C C C C C C C C C C C C C C Sector SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 130000 - 137FFF 138000 - 13FFFF 140000 - 147FFF 148000 - 14FFFF 150000 - 157FFF 158000 - 15FFFF 160000 - 167FFF 168000 - 16FFFF 170000 - 177FFF 178000 - 17FFFF 180000 - 187FFF 188000 - 18FFFF 190000 - 197FFF 198000 - 19FFFF 1A0000 - 1A7FFF 1A8000 - 1AFFFF 1B0000 - 1B7FFF 1B8000 - 1BFFFF 1C0000 - 1C7FFF 1C8000 - 1CFFFF 1D0000 - 1D7FFF 1D8000 - 1DFFFF 1E0000 - 1E7FFF 1E8000 - 1EFFFF 1F0000 - 1F7FFF 1F8000 - 1FFFFF 200000 - 207FFF 208000 - 20FFFF 210000 - 217FFF 218000 - 21FFFF 220000 - 227FFF 228000 - 22FFFF 230000 - 237FFF 238000 - 23FFFF 240000 - 247FFF 248000 - 24FFFF 250000 - 257FFF 258000 - 25FFFF 260000 - 267FFF 268000 - 26FFFF 270000 - 277FFF 278000 - 27FFFF 280000 - 287FFF 288000 - 28FFFF 290000 - 297FFF
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Memory Organization - 64-Mbit Bottom Boot (Continued)
x16 Plane C C C C C C C C C C C C D D D D D D D D D D D Sector SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 298000 - 29FFFF 2A0000 - 2A7FFF 2A8000 - 2AFFFF 2B0000 - 2B7FFF 2B8000 - 2BFFFF 2C0000 - 2C7FFF 2C8000 - 2CFFFF 2D0000 - 2D7FFF 2D8000 - 2DFFFF 2E0000 - 2E7FFF 2E8000 - 2EFFFF 2F0000 - 2F7FFF 2F8000 - 2FFFFF 300000 - 307FFF 308000 - 30FFFF 310000 - 317FFF 318000 - 31FFFF 320000 - 327FFF 328000 - 32FFFF 330000 - 337FFF 338000 - 33FFFF 340000 - 347FFF 348000 - 34FFFF Plane D D D D D D D D D D D D D D D D D D D D D D Sector SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K
Memory Organization - 64-Mbit Bottom Boot (Continued)
x16 Address Range (A21 - A0) 350000 - 357FFF 358000 - 35FFFF 360000 - 367FFF 368000 - 36FFFF 370000 - 377FFF 378000 - 37FFFF 380000 - 387FFF 388000 - 38FFFF 390000 - 397FFF 398000 - 39FFFF 3A0000 - 3A7FFF 3A8000 - 3AFFFF 3B0000 - 3B7FFF 3B8000 - 3BFFFF 3C0000 - 3C7FFF 3C8000 - 3CFFFF 3D0000 - 3D7FFF 3D8000 - 3DFFFF 3E0000 - 3E7FFF 3E8000 - 3EFFFF 3F0000 - 3F7FFF 3F8000 - 3FFFFF
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Memory Organization - 64-Mbit Top Boot
x16 Plane D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D C C C C C C C C C C C C C Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 00000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF 58000 - 5FFFF 60000 - 67FFF 68000 - 6FFFF 70000 - 77FFF 78000 - 7FFFF 80000 - 87FFF 88000 - 8FFFF 90000 - 97FFF 98000 - 9FFFF A0000 - A7FFF A8000 - AFFFF B0000 - B7FFF B8000 - BFFFF C0000 - C7FFF C8000 - CFFFF D0000 - D7FFF D8000 - DFFFF E0000 - E7FFF E8000 - EFFFF F0000 - F7FFF F8000 - FFFFF 100000 - 107FFF 108000 - 10FFFF 110000 - 117FFF 118000 - 11FFFF 120000 - 127FFF 128000 - 12FFFF 130000 - 137FFF 138000 - 13FFFF 140000 - 147FFF 148000 - 14FFFF 150000 - 157FFF 158000 - 15FFFF 160000 - 167FFF
Memory Organization - 64-Mbit Top Boot (Continued)
x16 Plane C C C C C C C C C C C C C C C C C C C B B B B B B B B B B B B B B B B B B B B B B B B B B Sector SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 168000 - 16FFFF 170000 - 177FFF 178000 - 17FFFF 180000 - 187FFF 188000 - 18FFFF 190000 - 197FFF 198000 - 19FFFF 1A0000 - 1A7FFF 1A8000 - 1AFFFF 1B0000 - 1B7FFF 1B8000 - 1BFFFF 1C0000 - 1C7FFF 1C8000 - 1CFFFF 1D0000 - 1D7FFF 1D8000 - 1DFFFF 1E0000 - 1E7FFF 1E8000 - 1EFFFF 1F0000 - 1F7FFF 1F8000 - 1FFFFF 200000 - 207FFF 208000 - 20FFFF 210000 - 217FFF 218000 - 21FFFF 220000 - 227FFF 228000 - 22FFFF 230000 - 237FFF 238000 - 23FFFF 240000 - 247FFF 248000 - 24FFFF 250000 - 257FFF 258000 - 25FFFF 260000 - 267FFF 268000 - 26FFFF 270000 - 277FFF 278000 - 27FFFF 280000 - 287FFF 288000 - 28FFFF 290000 - 297FFF 298000 -29FFFF 2A0000 - 2A7FFF 2A8000 - 2AFFFF 2B0000 - 2B7FFF 2B8000 - 2BFFFF 2C0000 - 2C7FFF 2C8000 - 2CFFFF
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Memory Organization - 64-Mbit Top Boot (Continued)
x16 Plane B B B B B B A A A A A A A A A A A A A A A A A Sector SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 2D0000 - 2D7FFF 2D8000 - 2DFFFF 2E0000 - 2E7FFF 2E8000 - 2EFFFF 2F0000 - 2F7FFF 2F8000 - 2FFFFF 300000 - 307FFF 308000 - 30FFFF 310000 - 317FFF 318000 - 31FFFF 320000 - 327FFF 328000 - 32FFFF 330000 - 337FFF 338000 - 33FFFF 340000 - 347FFF 348000 - 34FFFF 350000 - 357FFF 358000 - 35FFFF 360000 - 367FFF 368000 - 36FFFF 370000 - 377FFF 378000 - 37FFFF 380000 - 387FFF Plane A A A A A A A A A A A A A A A A A A A A A A Sector SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 4K 4K 4K 4K 4K 4K 4K 4K
Memory Organization - 64-Mbit Top Boot (Continued)
x16 Address Range (A21 - A0) 388000 - 38FFFF 390000 - 397FFF 398000 - 39FFFF 3A0000 - 3A7FFF 3A8000 - 3AFFFF 3B0000 - 3B7FFF 3B8000 - 3BFFFF 3C0000 - 3C7FFF 3C8000 - 3CFFFF 3D0000 - 3D7FFF 3D8000 - 3DFFFF 3E0000 - 3E7FFF 3E8000 - 3EFFFF 3F0000 - 3F7FFF 3F8000 - 3F8FFF 3F9000 - 3F9FFF 3FA000 - 3FAFFF 3FB000 - 3FBFFF 3FC000 - 3FCFFF 3FD000 - 3FDFFF 3FE000 - 3FEFFF 3FF000 - 3FFFFF
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DC and AC Operating Range
64-Mbit Device - 70, 85 ns Operating Temperature (Case) VCC Power Supply Industrial -40C - 85C 2.7V - 3.6V
Operating Modes
Mode Read Burst Read Program/Erase
(3)
CE VIL VIL VIL VIH X
OE VIL VIL VIH X
(1)
WE VIH VIH VIL X VIH X X X X
RESET VIH VIH VIH VIH VIH VIH X VIH VIL
VPP(4) X X VIHPP(5) X X X VILPP(6) X X
Ai Ai Ai Ai X
I/O DOUT DOUT DIN High Z
Standby/Program Inhibit
X VIL X VIH X
Program Inhibit
X X
Output Disable Reset Product Identification Software
Notes: 1. X can be VIL or VIH.
X X
High Z X High Z
VIH
A0 = VIL, A1 - A21 = VIL A0 = VIH, A1 - A21 = VIL
Manufacturer Code(3) Device Code(3)
2. 3. 4. 5. 6.
Refer to AC programming waveforms. Manufacturer Code: 001FH; Device Code: 00D6H - Bottom Boot; 00D2H - Top Boot. The VPP pin can be tied to VCC. For faster program/erase operations, VPP can be set to 12.0V 0.5V. VIHPP (min) = 1.65V. VILPP (max) = 0.8V.
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DC Characteristics
Symbol ILI ILO ISB1 ICC(1) ICCRE ICCRW VIL VIH VOL VOH Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Active Current VCC Read While Erase Current VCC Read While Write Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1 mA IOH = -100 A IOH = -400 A 2.5 V 2.4 2.0 0.45 Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCCQ - 0.3V to VCC f = 66 MHz; IOUT = 0 mA f = 66 MHz; IOUT = 0 mA f = 66 MHz; IOUT = 0 mA Min Max 1 1 35 30 50 50 0.6 Units A A A mA mA mA V V V
Note:
1. In the erase mode, ICC is 35 mA.
Input Test Waveforms and Measurement Level
2.0V AC DRIVING LEVELS 0.6V 1.5V AC MEASUREMENT LEVEL
tR, tF < 5 ns
Output Test Load
V CC 1.8K OUTPUT PIN 1.3K
30 pF
Pin Capacitance
f = 1 MHz, T = 25C(1)
Typ CIN COUT Note: 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V
1. This parameter is characterized and is not 100% tested.
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3441B-STKD-11/04
AC Asynchronous Read Timing Characteristics
64-Mbit-70 Symbol tACC tCE tOE tDF tRO Parameter Access, Address to Data Valid Access, CE to Data Valid OE to Data Valid CE, OE High to Data Float RESET to Output Delay Min Max 70 70 20 25 150 Min 64-Mbit-85 Max 85 85 20 25 150 Units ns ns ns ns ns
Asynchronous Read Cycle Waveform(1)(2)(3)
tRC A0 - A21 ADDRESS VALID
CE
tCE OE tOE tDF tACC tOH
RESET HIGH Z
tRO OUTPUT VALID
I/O0 - I/O15
Notes:
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
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AC Word Load Characteristics
Symbol tAS tAH tDS tDH tWP tWPH Parameter Address Setup Time to WE and CE Low Address Hold Time Data Setup Time Data Hold Time CE or WE Low Pulse Width CE or WE High Pulse Width Min 0 20 20 0 35 25 Max Units ns ns ns ns ns ns
AC Word Load Waveforms
WE Controlled
CE
I/O0-I/O15
DATA VALID
A0 -A21 tDS tDH tAH tAS WE tWP
CE Controlled
WE
I/O0-I/O15
DATA VALID
A0 -A21 tDS tAS CE tAH tWP tDH
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3441B-STKD-11/04
Program Cycle Characteristics
Symbol tBP tBPVPP tSEC1 tSEC2 tES tPS Parameter Word Programming Time (Vpp = VCC) Word Programming Time (VPP > 11.5V) Sector Erase Cycle Time (4K word sectors) Sector Erase Cycle Time (32K word sectors) Erase Suspend Time Program Suspend Time Min Typ 22 10 100 500 15 10 Max Units s s ms ms s s
Program Cycle Waveforms
OE(1) CE
I/O0 -I/O15
XXAA
XX55
XXA0
INPUT DATA
A0 -A21
555
AAA
555
ADDR
WE
Sector, Plane or Chip Erase Cycle Waveforms
OE(1)
CE
I/O0 -I/O15
XXAA
XX55
XX80
XXAA
XX55
Note3
A0 -A21
555
AAA
555
555
AAA
Note2
WE
Notes:
1. OE must be high only when WE and CE are both low. 2. For chip erase, the address should be 555. For plane or sector erase, the address depends on what plane or sector is to be erased. (See note 4 and 6 under Command Definitions on page 12.) 3. For chip erase, the data should be XX10H, for plane erase, the data should be XX20H, and for sector erase, the data should be XX30H 4. The waveforms shown above use the WE controlled AC Word Load Waveforms.
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Data Polling Characteristics
Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay(2) Write Recovery Time 0 Min 10 10 Typ Max Units ns ns ns ns
1. These parameters are characterized and not 100% tested. 2. See tOE spec on page 20.
Data Polling Waveforms
WE CE OE I/O7 A0-A21
Toggle Bit Characteristics(1)
Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay(2) OE High Pulse Write Recovery Time 50 0 Min 10 10 Typ Max Units ns ns ns ns ns
1. These parameters are characterized and not 100% tested. 2. See tOE spec on page 20.
Toggle Bit Waveforms(1)(2)(3)
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary.
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3441B-STKD-11/04
Table 4. Common Flash Interface Definition for 64-Mbit Device
Address 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 64-Mbit Device 0051h 0052h 0059h 0002h 0000h 0041h 0000h 0000h 0000h 0000h 0000h 0027h 0031h 00B5h 00C5h 0004h 0000h 0009h 0010h 0004h 0000h 0003h 0003h 0017h 0001h 0000h 0000h 0000h 0002h 007Eh 0000h 0000h 0001h 0007h 0000h 0020h 0000h Typ block erase - 500 ms Typ chip erase, 64,300 ms Max word write/typ time n/a Max block erase/typ block erase Max chip erase/ typ chip erase Device size x16 device x16 device Multiple byte write not supported Multiple byte write not supported 2 regions, x = 2 64K bytes, Y = 126 64K bytes, Y = 126 64K bytes, Z = 256 64K bytes, Z = 256 8K bytes, Y = 7 8K bytes, Y = 7 8K bytes, Z = 32 8K bytes, Z = 32 VCC min write/erase VCC max write/erase VPP min voltage VPP max voltage Typ word write - 16 s Comments "Q" "R" "Y"
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Table 4. Common Flash Interface Definition for 64-Mbit Device (Continued)
Address 64-Mbit Device Comments VENDOR SPECIFIC EXTENDED QUERY 41h 42h 43h 44h 45h 46h 0050h 0052h 0049h 0031h 0030h 008Fh "P" "R" "I" Major version number, ASCII Minor version number, ASCII Bit 0 - chip erase supported, 0 - no, 1 - yes Bit 1 - erase suspend supported, 0 - no, 1 - yes Bit 2 - program suspend supported, 0 - no, 1 - yes Bit 3 - simultaneous operations supported, 0 - no, 1 - yes Bit 4 - burst mode read supported, 0 - no, 1 - yes Bit 5 - page mode read supported, 0 - no, 1 - yes Bit 6 - queued erase supported, 0 - no, 1 - yes Bit 7 - protection bits supported, 0 - no, 1 - yes Bit 0 - top ("0") or bottom ("1") boot block device Undefined bits are "0" Bit 0 - 4 word linear burst with wrap around, 0 - no, 1 - yes Bit 1 - 8 word linear burst with wrap around, 0 - no, 1 - yes Bit 2 - continuos burst, 0 - no, 1 - yes Undefined bits are "0" Bit 0 - 4 word page, 0 - no, 1 - yes Bit 1 - 8 word page, 0 - no, 1 - yes Undefined bits are "0" Location of protection register lock byte, the section's first byte # of bytes in the factory prog section of prot register - 2*n # of bytes in the user prog section of prot register - 2*n
47h 48h
0000h Top Boot or 0001h Bottom Boot 0000h
49h
0000h
4Ah 4Bh 4Ch
0080h 0003h 0003h
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3441B-STKD-11/04
16-Mbit PSRAM Description
The device is a 16-Mbit 1T/1C PSRAM featured by high-speed operation and super low power consumption. The 16-Mbit device adopts one transistor memory cell and is organized as 1,048,576 words by 16 bits. It operates in the extended range of temperatures and supports a wide operating voltage range. The device also supports the deep powerdown mode for a super low standby current. * * * * *
CMOS Process Technology 1M x 16-bit Organization TTL Compatible and Tri-state Outputs Deep Power-down: Memory Cell Data Hold Invalid Data Mask Function by LB, UB
Power Dissipation (Max) Mode CS1 with UB, LB:tOE(1) (ISB1) 85 A (IDPD) 10 A (ICC2) 25 mA
Features
Product 16-Mbit PSRAM
Voltage [V] 2.7 ~ 3.1
Speed tRC [ns] 70
Temp. [C] -30 ~ 85
Note:
1. tOE - UB, LB = High:Output Disable.
Block Diagram
A0 ROW DECODER
SENSE AMP
I/O1
COLUMN DECODER
DATA I/O BUFFER
PRE DECODER
ADD INPUT BUFFER
I/O8 I/O9
MEMORY ARRAY 1,024K X 16
WRITE DRIVER
BLOCK DECODER
I/O16
A19
CS1 CS2 PSWE PSOE LB UB
CONTROL LOGIC
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Absolute Maximum Ratings(1)
Symbol VIN, VOUT VCC TA TSTG PD TSOLDER Note: Parameter Input/Output Voltage Power Supply Ambient Temperature Storage Temperature Power Dissipation Ball Soldering Temperature and Time Rating -0.3 to VCC +0.3 -0.5 to 3.6 -30 to 85 -55 to 150 1.0 260*10 Unit V V C C W C*sec
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability.
Truth Table
I/O Pin CS1 H X L
(1)
CS2 H L H H H H H H H H
PSWE X X X H H H H L L L
PSOE X X X H L L L X X X
LB(2) X X H X L H L L H L
UB X X H X H L L H L L
Mode Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
I/O1 ~ I/O8 High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN
I/O9 ~ I/O16 High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN
Power Standby Deep Power-down Active Active Active Active Active Active Active Active
(1)
(1)
L L L L L L L Notes:
1. H = VIH, L = VIL, X = Don't Care (VIL or VIH). 2. UB, LB (Upper, Lower Byte Enable). These active LOW inputs allow individual bytes to be written or read. When LB is LOW, data is written or read to the lower byte, I/O1 - I/O8. When UB is LOW, data is written or read to the upper byte, I/O9 I/O116.
Recommended DC Operating Condition
Symbol VCC GND VIH VIL
(1)
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage
Min 2.7 0 2.2 -0.3
(1)
Typ 2.9
Max 3.1 0 VCC + 0.3 0.6
Unit V V V V
Note:
1. VIL = -1.5V for pulse width less than 10 ns. Undershoot is sampled, not 100% tested.
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3441B-STKD-11/04
DC Electrical Characteristics
VCC = 2.7V - 3.1V, TA = -30C to 85C (I)
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition GND < VIN < VCC GND < VOUT < VCC, CS1 = VIH, CS2 = VIH, PSOE = VIH or PSWE = VIL CS1 = VIL, CS2 = VIH, VIN = VIH or VIL, II/O = 0 mA CS1 < 0.2V, CS2 > VCC - 0.2V VIN < 0.2V or VIN > VCC - 0.2V, Cycle Time = 1 s 100% Duty, II/O = 0 mA CS1 = VIL, CS2 = VIH, VIN = VIH or VIL, Cycle Time = Min 100% Duty, II/O = 0 mA TTL Standby Current Standby Current (CMOS Input) Deep Power-down Current Output Low Voltage Output High Voltage CS1, CS2 = VIH or UB, LB = VIH CS1, CS2 > VCC - 0.2V or CS2 < GND +0.2V IOL = 0.5 mA IOH = -0.5 mA VCC - 0.3 Min -1 -1 Max 1 1 Unit A A
ICC ICC1
Operating Power Supply Current Average Operating Current
3 5
mA mA
ICC2
25
mA
ISB ISB1 IDPD VOL VOH
0.5 85 10 0.3
mA A A V V
Capacitance(1)
(Temp = 25C, f = 1.0 MHz)
Symbol CIN COUT Note: Parameter Input Capacitance (Add, CS1, CS2, PSWE, PSOE, UB, LB) Output Capacitance (I/O) Condition VIN = 0V VI/O = 0V Max 8 10 Unit pF pF
1. These parameters are sampled and not 100% tested.
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AC Characteristics
VCC = 2.7V ~ 3.1V, TA = -30C to 85C (I), Unless Otherwise Specified
70 ns # Read Cycle 1 2 3 4 5 6 7 8 9 10 11 12 Write Cycle 13 14 15 16 17 18 19 20 21 22 23 tWC tCW tAW tBW tAS tWP tWR tWHZ tDW tDH tOW Write Cycle Time Chip Selection to End of Write Address Valid to End of Write LB, UB Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 70 60 60 60 0 50 0 0 30 0 5 20 ns ns ns ns ns ns ns ns ns ns ns tRC tAA tACS tOE tBA tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tOH Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid LB, UB Access Time Chip Select to Output in Low Z Output Enable to Output in Low Z LB, UB Enable to Output in Low Z Chip Disable to Output in High Z Out Disable to Output in High Z LB, UB Disable to Output in High Z Output Hold from Address Change 10 5 10 0 0 0 5 10 10 10 70 70 70 20 20 ns ns ns ns ns ns ns ns ns ns ns ns Symbol Parameter Min Max Unit
AC Test Conditions
TA = -30C to 85C (M), Unless Otherwise Specified
Parameter Input Pulse Level Input Rising and Fall Time Input and Output Timing Reference Level Output Load Value 0.4V to 2.2V 5 ns 0.5 * VCC (See AC Test Loads Figure on page 30)
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3441B-STKD-11/04
AC Test Loads
RL = 50 Ohm DOUT Z0 = 50 Ohm CL = 50 pF
(1)
VL = 0.5*VCCQ
Note:
Including jig and scope capacitance.
Power-up Sequence Deep Power-down Entry Sequence Deep Power-down Exit Sequence State Diagram
1. Supply power. 2. Maintain stable power for longer than 200 s. 1. Keep CS2 low state. Deep Power-down mode is maintained while CS2 is low state.
1. Keep CS2 high state. 2. Maintain stable power for longer than 200 s.
Power On
Power-up Sequence Wait 200 s
CS2 = VIH
Active CS1 = VIL, CS2 = VIH CS2 = VIH, CS1 = VIH Standby Mode CS2 = VIL Deep Powerdown Mode CS2 = VIL
Deep Power-down Exit Sequence
Deep Power-down Entry Sequence
Standby Mode Characteristics
Mode Standby Deep Power-down Memory Cell Data Valid Invalid Standby Current [A] 85 10 Wait Time [s] 0 200
30
AT52BC6402A(T)
3441B-STKD-11/04
AT52BC6402A(T)
Timing Diagrams
Power-up Sequence Timing
Wait 200 s
VCC CS2 CS1
Note: Power-up time is defined when CS2 is kept high before VCC reaches specified minimum level. In case of CS2 is switched from low level to high level, after VCC reached specified level, it is defined as the deep power-down exit.
Normal Operation
Deep Power-down Entry/Exit Sequence Timing
Suspend 1 s Deep Power-down Mode
CS2 CS1
Wait 200 s
Normal Operation
Note:
When switching CS2 from high level to low level, the device will be in the deep power-down. In this case, an internal refresh stops and the data might be lost.
Standby Mode Characteristics Timing
tRC
CS1 ISB1
Standby Mode
Deep Power-down Mode Characteristics Timing
Suspend 1 s
CS2
Deep Power-down Mode
IDPD
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3441B-STKD-11/04
Read Cycle 1(1),(4)
tRC ADDRESS tAA CS1 CS2 tACS tCHZ(3) VIH tBA tBHZ(3) PSOE tOLZ(3) tBLZ(3) tCLZ(3) DATA OUT HIGH-Z DATA VALID tOE tOHZ (3) tOH
UB, LB
Read Cycle 2, CS2 = VIH(1),(2),(4)
tRC ADDRESS tAA tOH DATA OUT PREVIOUS DATA DATA VALID tOH
Read Cycle 3, CS2 = VIH(1),(2),(4)
CS1 tACS tCLZ DATA OUT
Notes:
HIGH-Z
(3)
tCHZ (3)
DATA VALID
1. Read Cycle occurs whenever a high on the PSWE and PSOE is low, while UB and/or LB and CS1 and CS2 are in active status. 2. PSOE = VIL. 3. The tCHZ, tBHZ and tOHZ are defined as the time at which the outputs achieve the high impedance state and tOLZ, tBLZ and tCLZ are defined as the time at which the outputs achieve the low impedance state. These are not referenced to output voltage levels. 4. CS1 in high for the standby, low for active.
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AT52BC6402A(T)
Write Cycle 1 (PSWE Controlled)(1),(4),(5),(9),(10)
tWC
ADDRESS
tCW tWR(2)
CS1 CS2
VIH
tAW tBW
UB,LB PSWE
HIGH-Z tWHZ(3)(8) tWP tAS tDW
DATA VALID
tDH tOW
DATA IN DATA OUT
(6)
(7)
Write Cycle 2 (CS1 Controlled)(1),(4),(5),(9),(10)
tWC
ADDRESS
tAS tCW tWR(2)
CS1 CS2
VIH
tAW tBW
UB, LB PSWE
HIGH-Z HIGH-Z tWP tDW tDH
DATA IN DATA OUT
Notes:
DATA VALID
1. A write occurs during the overlap of a low CS1, a low PSWE, and a low UB or LB. 2. tWR is measured from the earlier of CS1 or PSWE going high to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the CS1, LB and UB low transition occur simultaneously with the PSWE low transition or after the PSWE transition, outputs remain in a high impedance state. 5. PSOE is continuously low (PSOE = VIL). 6. Q (data out) is the invalid data. 7. Q (data out) is the read data of the next address. 8. The tWHZ is defined as the time at which the outputs achieves the high impedance state. It is not referenced to output voltage levels. 9. CS1 in high for the standby, low for active. 10. Do not input data to the I/O pins while they are in the output state.
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3441B-STKD-11/04
Write Cycle 3 (LB, UB Controlled)
tWC
ADDRESS
tCW
tWR
CS1 CS2
tAS
VIH
tAW tAS tBA tWP tDW
tWR
UB, LB PSWE
HIGH-Z
tAS
tDH
DATA IN
Notes:
DATA VALID
1. The tBW is specified from the time satisfied both tAS and tWR. 2. Although UB and LB are high state, it's illegal function to change address both CS and PSWE are in low state.
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AT52BC6402A(T)
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AT52BC6402A(T)
Avoid Timing
The 16-Mbit PSRAM has a timing which is not supported at read operation. If your system has multiple invalid address signal shorter than t RC during over 48 s at read operation which showed in abnormal timing, it needs a normal read timing at least during 48 s which showed in Avoidable Timing(1) or toggle the CS1 to high (> tRC) one time at least which showed in Avoidable Timing(2)
Abnormal Timing
CS1
PSWE
< tRC
> 48 s
ADDRESS
Avoidable Timing (1)
CS1
PSWE
> 48 s
> tRC
ADDRESS
Avoidable Timing (2)
> tRC
CS1
PSWE
< tRC
> 48 s
ADDRESS
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3441B-STKD-11/04
Ordering Information
tACC (ns) Ordering Code AT52BC6402A-70CI 70 AT52BC6402AT-70CI AT52BC6402A-85CI 85 AT52BC6402AT-85CI Top 1M x 16 66C6 Top Bottom 1M x 16 1M x 16 66C6 66C6 Flash Boot Block Bottom PSRAM 1M x 16 Package 66C6
Operation Range
Industrial (-40 to 85C) Industrial (-40 to 85C) Industrial (-40 to 85C) Industrial (-40 to 85C)
Package Type 66C6 66-ball, Plastic Chip-size Ball Grid Array Package (CBGA)
36
AT52BC6402A(T)
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AT52BC6402A(T)
Packaging Information
66C6 - CBGA
0.12 C
D
C Seating Plane Marked A1 Identifier
Side View
E
A1
Top View
A
1.10 REF
12 11 10 9 8
D1
7 6 5 4 3 2 1
A1 Ball Corner
A
e
B C D
E1
E F G H
1.20 REF e Ob SYMBOL A
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.17 10.90 NOM - - 11.00 8.80 TYP 7.90 8.00 5.60 TYP 0.80 TYP 0.40 TYP 8.10 MAX 1.0 - 11.10 NOTE
Bottom View
A1 D D1 E E1 e
Ob
08/27/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 66C6, 66-ball (12 x 8 Array), 11 x 8 x 1.0 mm Body, 0.8 mm Ball Pitch Chip-scale Ball Grid Array Package (CBGA) DRAWING NO. 66C6 REV. A
R
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3441B-STKD-11/04
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3441B-STKD-11/04 xM

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